The present invention relates generally to semiconductor devices, and more specifically to power insulated gate devices including MOSFETs (MOS field effect transistors and IGBTs (insulated gate bipolar transistors).
In controlling the application of electrical power to a load, it is a known practice to use a switching device in series with the load. Power MOS devices have proved very useful in this regard. The terms MOS (which originally stood for Metal-Oxide-Semiconductor) and MOSFET are used to refer to insulated gate devices generally, not withstanding the fact most modern devices have polysilicon gates rather than metal gates.
A power MOS device is often implemented as an array of switching cells (perhaps 10,000 in number) formed on a single chip, with each cell defining a microscopically small insulated gate transistor. In the case of MOSFET cells, respective gates, drains, and sources of the cells are connected in parallel to define the power MOSFET. In the case of IGBT cells, the respective gates, emitters, and collectors of the cells are connected in parallel to define the power IGBT.
During operation it is often desirable to sense various of the device's operating parameters, such as the current through the device and load, the voltage across the device, the power dissipated in the device, and the temperature of the device. The results of such sensing can be used to detect device and load efficiency, short circuit conditions, meltdown conditions, and the like.
U.S. Pat. No. 4,931,844, issued June 5, 1990, the disclosure of which is hereby incorporated by reference, describes the use of a current mirror technique for providing voltage, current, power, resistance and temperature sensing capability. In brief, the current mirror technique provides a relatively small number of cells on the chip, referred to as mirror cells, with their respective terminals connected in common with each other to define a monolithically formed sense transistor (also referred to as a mirror transistor, a current mirror, or simply a mirror).
In a typical current mirror configuration, the respective drain nodes of the main transistor and the sense transistor are connected together, and the respective gate nodes of main transistor and the sense transistor are connected together. A resistor is connected between the main transistor source node and the sense transistor source node. Assuming that the resistor has a resistance that is small compared to the on-resistance of the sense transistor, the voltage across the resistor will provide an indication of the current flowing through the sense transistor.
The sense transistor current is a known fraction of the main transistor current, being lower by a factor generally commensurate with the ratio of the number of sense transistor cells to main transistor cells. Actually the sense transistor current is generally proportionately larger.
In the forementioned U.S. Pat. No. 4,931,844, the temperature of the chip is determined by calculating the on-resistance of the chip and correlating that value with the known temperature dependence of the on-resistance. The on-resistance is determined from the voltage and current in the main transistor as determined on the basis of the sense transistor current. That approach is useful for measuring the temperature when the main transistor is in the conducting or on state.
Another approach to temperature sensing is shown in M. Glogolja, "Built in protection makes TEMPFET resistant to catastrophic failures," PCIM, March 1989, pp. 19-23. This approach provides an extra chip that is die attached to the top surface of the power device for temperature sensing. However, this solution may be unreliable, possibly adding contamination to the main power die if not carried out under scrupulously controlled conditions.